Wen Chieh (Laurent) Lo
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I received my bachelor’s degree in Electrical Engineering from National Taiwan University in 2024. I am applying for the ECE/CSE Graduate Program for Fall 2025.
My research interests are in VLSI and Computer Architecture.
I was a summer intern at MediaTek’s SoC Integration Department, where I designed a low-power architecture plan for the NoC structure.
During my undergraduate studies, I was advised by Prof. Yi-Chang Lu on Spliced Genomic Sequence Hardware Acceleration research and developed resource-efficient Machine Learning Model Deployment on FPGA features in Prof. Ryan Kastner’s Lab.
Research Interests
- VLSI Design
- Computer Architecture
- Digital Circuit Design