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B.S. in Electrical Engineering

National Taiwan University

VLSI / Computer Architecture

• Computer-aided VLSI System Design
• Computer Architecture
• Digital Circuit Design Lab
• Integrated Circuit Design
• Operating System
• Algorithm
• Data Structure
• Computer Vision
• Machine Learning
• Linear Algebra
• Discrete Math
• CUDA Parallel Programming

Digital IC Design Summer Intern

MediaTek Inc., Taipei

Designed NoC IP low-power clock control flow using clock management IP

• Designed a dynamic clock control flow for Network-on-Chip (NoC) nodes with dynamic clock management IP, optimizing power efficiency and preventing packet transmission conflicts by ensuring no other packets are being transmitted during clock transitions.
• Developed a signaling mechanism to prevent data loss during clock restart, while supporting reliable transmission across different clock domains within the NoC system.
• Maintained the synthesis environment for performance, power, and area analysis of the Configuration BUS.

Undergraduate Researcher

Prof. Yi-Chang Lu's Lab, National Taiwan University

Designing the first memory-efficient syncmer-based end-to-end hardware-accelerated genome sequence aligner

• Designed the first memory-efficient syncmer-based end-to-end hardware-accelerated genome sequence aligner, achieving 12.84x speedup compared to minimap2 using TSMC 28nm process and 3.10x speedup using FPGA.
• Designed the first-ever hardware-friendly syncmer extraction hardware, utilizing FIFO and a 2-stage buffer to enable pipelined dual-parameter offset syncmer extraction.
• Performed bitwidth reduction for alignment traceback, optimizing spliced alignment by storing traceback information with only 5 bits and using a heuristic to omit intermediate storage for long introns, reducing over 98% of memory usage.

Undergraduate Researcher

Prof. Ryan Kastner's Lab, UC San Diego

Developed an automatic bitwidth selection feature for HLS4ML, a real-time machine learning model inference toolkit.

• Developed an automatic accumulator bitwidth optimization feature for the HLS4ML real-time machine learning model inference toolkit for both Fully Connected and Convolutional layers, leveraging the wrap-around property to ensure efficient resource utilization and overflow prevention.
• Established precision bounds (Pessimistic, Conservative, and Optimistic) based on weight data, input data, and kernel specifications, using a custom method to enable flexible bitwidth configurations for diverse neural network architectures.

2021 Xilinx PYNQ AI/IoT Hackathon 2nd Place

Project Topic: An Efficient Approach for Traffic Flow Detection and Tracking